data brief for further information contact your local stmicroelectronics sales office. november 2008 rev 1 1/4 4 STEVAL-ISA050V1 monolithic vr for chipset and ddr2/3 demonstration board based on the pm6641 features switching section ? 0.8 v 1% voltage reference ? 2.7 v to 5.5 v input voltage range ? fast response, constant frequency, current mode control ? three independent, adjustable, smps for ddr2/3 (vddq) and chipset supply ? s3-s5 states compliant ddr2/3 section ? active soft-end for all outputs ? selectable tracking discharge for vddq ? separate power good signals ? pulse skipping at light load ? programmable current limit and soft-start for all outputs ? latched ovp, uvp protection ? thermal protection reference and termination voltages (vttref and vtt) ? 2 apk ldo for ddr2/3 termination (vtt) with fold back ? remote vtt output sensing ? high-z vtt output in s3 ? 15 ma low noise ddr2/3 buffered reference (vttref) application supply for ultra-mobile pc (umpc) description the STEVAL-ISA050V1 demonstration board is based on the pm6641, that is a monolithic voltage regulator module, with internal power mosfet, specifically designed to supply ddr2/3 memory and chipset in ultra-mobile pc and real estate portable systems. it integrates three independent, adjustable, constant frequency buck converters, a 2 apk low drop-out (ldo) linear regulator and a 15 ma low noise buffered reference. each regulator is provided of basic under voltage (uv) and over voltage (ov) protections, programmable soft-start and current limit, active soft-end and pulse-skipping at light loads. STEVAL-ISA050V1 www.st.com
circuit schematic STEVAL-ISA050V1 2/4 1 circuit schematic figure 1. schematic c 2 6 060 0 6 0 3 -100p - 1 0 0 p c 4 08 0 8 0 5 -10u - 1 0 u c 1 6 06 0 6 0 3 - 1 0 0n 0 n c 2 7 06 0 6 0 3 - 1 0 0p 0 p r 1 0 0 6 03- 0 3 - 1 80k 8 0 k t p 8 g n d 1 r 2 0 0 603- 6 0 3 - 6 8k 8 k t p 6 a g n d 1 c 2 8 06 0 6 0 3 -10 - 1 0 0 p r 2 06 0 6 0 3-4 3 - 4 r 3 v i n t p 1 6 a g n d 1 c 1 8 0603 0 6 0 3 - 33 3 3 n v c c t p 15 1 5 l d o i n 1 c 3 0 0603 0 6 0 3 - 100 1 0 0 p v c c av a v c c c 1 9 06 0 6 0 3 -22n - 2 2 n c 7 b c a s e - 220u 2 2 0 u t p 4 p g _1 _ 1 s 05 0 5 1 c 3 1 0 6 03-1 0 3 - 1 0 0 p + c 1 3 e l s m d c - 10 1 0 u 1 2 r 3 3 0 603 6 0 3 - j o i n a v c c t p 12 1 2 v o u t _ 1 s 0 5 1 c 2 08 0 8 0 5-1 5 - 1 0 u av a v c c r 1 2 0 603- 6 0 3 - 4 7k 7 k r 3 0603 0 6 0 3 - 100 1 0 0 k t p 14 1 4 v t t 1 r 4 0603 0 6 0 3 - 68 6 8 k c 6 b c a s e - 2 20 2 0 u c 1 7 0 6 03-1 0 3 - 1 0 0 n t p 5 v c c 1 r 1 1 0603 0 6 0 3 - 100 1 0 0 k + c 5 e l s m d c - 10u 1 0 u 1 2 c 2 1 0 603 6 0 3 - 22 2 2 n r 1 7 0 6 03- 0 3 - 6 8 k c 2 5 0 603 6 0 3 - 100 1 0 0 p t p 1 v t t r e f 1 c 3 2 0 603 6 0 3 - 15 1 5 p j p 1 s t r i p 3 1 3 2 r 3 1 0 6 03-joi 0 3 - j o i n c 1 1 1 206 2 0 6 - 22 2 2 u 1 2 t p 13 1 3 g n d 1 j p 3 s t r i p 3 1 3 2 r 3 4 06 0 6 0 3-joi 3 - j o i n u 1 p m 66 6 6 4 1_q 1 _ q f p n a g n d _1 _ 1 1 se s e t _ s w f 2 v o u t _ 1 s 8 3 c s n s 4 s g n d _ 1 s 8 _ 1 5 s g n d _ 1 s 8 _ 2 6 vs v s w _ 1 s 8_1 8 _ 1 7 vs v s w _ 1 s 8_2 8 _ 2 8 v i n _ 1 s 8 _1 _ 1 9 v i n _ 1 s 8 _2 _ 2 1 0 v f b _ 1 s 8 1 1 c o m p _ 1 s 8 1 2 s s _ 1 s 8 1 3 s s _ 1 s 0 5 1 4 c o m p _ 1 s 0 5 1 5 v f b _1 _ 1 s 0 5 1 6 s g nd n d _1 _ 1 s 0 5 _ 1 1 7 v s w _ 1 s 0 5_1 5 _ 1 1 9 v s w _ 1 s 0 5_2 5 _ 2 2 0 v i n _1 _ 1 s 0 5 _ 2 2 2 p g _1 _ 1 s 0 5 2 3 p g _1 _ 1 s 8 2 4 e n _ v t t 3 6 e n _1 _ 1 s 5 3 5 e n _1 _ 1 s 05 0 5 3 4 v i n _1 _ 1 s 5 3 3 vs v s w _1 _ 1 s 5_2 5 _ 2 3 2 vs v s w _1 _ 1 s 5_1 5 _ 1 3 1 s g n d _1 _ 1 s 5_ 5 _ 2 3 0 s g n d _1 _ 1 s 5_ 5 _ 1 2 9 v f b _1 _ 1 s 5 2 8 c o m p _1 _ 1 s 5 2 7 s s _1 _ 1 s 5 2 6 p g _1 _ 1 s 5 2 5 s g nd n d _1 _ 1 s 0 5 _ 2 1 8 v i n _1 _ 1 s 0 5 _ 1 2 1 v c c 4 8 v t t _ f b 4 7 d s c g 4 6 v t t r e f 4 5 l d o _ i n 4 4 v t t 4 3 v t t _ g n d 4 2 a v c c 4 1 a g nd n d _ 2 4 0 se s e t _ p h 1 3 9 a g nd n d _ 3 3 8 e n _ 1 s 8 3 7 t h e r m a l 4 9 a v c c l 2 2839 2 8 3 9 - 1u 1 u 5 1 2 c 2 3 0 6 03- 0 3 - 4 70p 7 0 p l 3 283 2 8 3 9 - 1 u 1 2 r 1 9 060 0 6 0 3 -68k - 6 8 k + c 8 e l s m d c - 10u 1 0 u 1 2 t p 18 1 8 a u x 1 c 3 3 0603 0 6 0 3 - 15 1 5 p c 1 2 0 805 8 0 5 - 10 1 0 u t p 2 p g _ 1 s 8 1 av a v c c t p 7 v i n 1 c 1 5 b c a s e - 220u 2 2 0 u c 2 2 0603 0 6 0 3 - 330 3 3 0 p c 2 0 060 0 6 0 3 -22n - 2 2 n c 1 0603 0 6 0 3 - 1 u j p 4 s t r i p 3 1 3 2 l 1 2 8 39- 3 9 - 1 u 1 2 r 5 060 0 6 0 3 -15 - 1 5 0 k j p 5 s t r i p 3 1 3 2 r 7 0603 0 6 0 3 - 100 1 0 0 k r 8 0603 0 6 0 3 - 120 1 2 0 k r 3 2 06 0 6 0 3-joi 3 - j o i n + c 1 4 e l s m d c - 10u 1 0 u 1 2 a v c c t p 10 1 0 v o u t _ 1 s 5 1 t p 3 p g _ 1 s 5 1 c 3 4 06 0 6 0 3-1 3 - 1 5 p a u x a u x t p 9 v o u t _1 _ 1 s 8 1 r 2 1 0 603 6 0 3 - 68 6 8 k r 6 060 0 6 0 3 -12 - 1 2 0 k r 2 2 0 603 6 0 3 - 68 6 8 k j p 7 s t r i p 2 1 2 r 3 0 0603 0 6 0 3 - joi j o i n r 1 3 0 6 03- 0 3 - 6 8 k a u x t p 17 1 7 g n d 1 c 3 0805 0 8 0 5 - 10 1 0 u r 2 3 0 603 6 0 3 - 68 6 8 k j p 8 s t r i p 2 1 2 s w 1 s w d i p - 4 1 2 3 4 5 6 7 8 v i n c 2 4 0 6 03- 0 3 - 3 30p 3 0 p c 9 b c a s e - 220u 2 2 0 u r 1 8 060 0 6 0 3 -68k - 6 8 k c 1 0 b c a s e - 2 20 2 0 u r 1 06 0 6 0 3-4 3 - 4 r 3 t p 11 1 1 g n d 1 v i n c 2 9 06 0 6 0 3 -10 - 1 0 0 p j p 6 s t r i p 3 1 3 2 r 9 0 6 03- 0 3 - 5 6k 6 k am0 3 2 8 6v1
STEVAL-ISA050V1 revision history 3/4 2 revision history table 1. document revision history date revision changes 12-nov-2008 1 initial release.
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